Seminar of Institute of Information Systems and Applications

Abstract

Negative-Bias Temperature Instability (NBTI) has become one of the most drastic reliability threats in modern IC designs. To tolerance NBTI on multi-core systems, previous researchers have proposed various task assignment and/or dynamic voltage frequency scaling algorithms. Most of the proposed methods maintain all cores in the multi-core system under similar aging conditions (symmetric aging). Although these methods can mitigate NBTI, the symmetric aging may reduce the lifetime of a multi-core system. If a critical task (i.e., a task with a tight timing constraint) arrives when the system has already operated for years, it is possible that none of the equivalently aged cores can complete the critical task within its timing constraints. This unavoidable timing failure then will shorten the lifetime of the system. With the above observation, this paper proposes a novel reliability improvement framework which realize the concept of asymmetric aging by task graph Retiming, task Ordering, task Assignment under asymmetric aging, and Dynamic voltage selection (ROAD) for multi-core systems. Experimental results show that our approach can significantly increase the system lifetime with no or insignificant energy overhead.

Bio:

Dr. Yu-Guang Chen received the B.S. degree and Ph.D. degree in Dept. of Computer Science from the National Tsing Hua University, Hsinchu, Taiwan, in 2009 and 2016, respectively.

In 2014, He was a visiting scholar at Kyoto University, Kyoto, Japan. In 2015, he was a lecturer at Missouri University of Science and Technology, MO, USA. In 2016, he was a research fellow in University of Notre Dame, IN, USA. From 2017 to 2019, he was with the faculty at the Department of Computer Science and Engineering, Yuan Ze University, Taoyuan, Taiwan. He is currently an Assistant Professor with the Department of Electrical Engineering, National Central University. He has served on the technical program committee of several conferences such as ASP-DAC and GLSVLSI. He also served as co-chair of CADathlon at ICCAD 2019.

His current research interests include low power design/optimization and reliability issues in computer-aided design, especially on power gating, DVFS, NBTI, and 3D-IC optimization.

All faculties and students are welcome to join.