Title: Modern Challenges for Global Routing and Detailed Placement

Speaker: Dr. Wen-Hao Liu, Cadence, USA

Date:103年12月25日(星期四)下午三點三十分

Place:資電館R224

Host:王廷基 老師

 Abstract:

As technology nodes advance, more and more manufacturing issues and design-specified requirements emerge.  This talk will introduce the modern challenges for global routing and detailed placement in the advanced technology nodes. Also, the speaker will share his experience about how to develop and maintain a commercial place-and-route tool, and introduce the requirements to global routing and detailed placement engines for production.

Speaker Bio:

Wen-Hao Liu received his B.S. and Ph.D. degree in computer science from National Chiao Tung University, Taiwan respectively in 2008 and 2013. He currently is working at Cadence, Austin, Taxes. His research interests include routing, placement, clock synthesis, and parallel computing. Wen-Hao had won the ISPD 2009 clock network synthesis contest, and he is the developer of NCTU-GR that is a well-known academic global router. Currently, Wen-Hao is serving on the review boards of IEEE TCAD, IEEE TVLSI, ACM TODASE, and Integration, the VLSI Journal.