Abstract:
Clock network synthesis for synchronous VLSI design is of crucial importance to performance since most (if not all) the functional units in the chip are coordinated by the clock signals. At the same time, power optimization in clock distribution is critical because of the size of the interconnect and its high switching activity. EDA research in clock optimization is highly related to the design styles and methodologies. As a result, clock optimization has been an independent set of tools in the design flow, and there is limited consideration in clock during the core placement, timing optimization and routing steps. Plenty of clock aware placement can be found in the literature but they are usually not widely adopted by industrial flow. In this talk, practical issues and concerns in clock-aware physical design will be discussed.
The presentation will focus on IBM's physical design flow on high-performance VLSI designs, especially on how to consider clock optimization in placement and timing optimization.
Speaker Bio:
Dr. Cliff Sze is a research scientist at the IBM T. J. Watson Research Center and the Austin Research Laboratory while he has contributed to the clocking/placement/routing tools for several IBM high performance ASIC designs, as well as POWER6, POWER7, z10, z196, Xbox 360 and the Sony/Toshiba/IBM CELL processors. He has conducted research on EDA for more than 15 years and has published over 50 technical papers in peer reviewed journals and conferences. He served as the general chair of International Symposium on Physical Design (ISPD) 2014, and was appointed as associate editor for ACM Transactions on Design Automation of Electronic Systems (TODAES). He is a recipient of the ACM Special Interest Group on Design Automation (SIGDA) technical leadership award, and has received several IBM technical/invention awards, filed more than 30 patents applications and was granted 20+ patents worldwide. Cliff received his B.Eng. and M.Phil. degrees from the Department of Computer Science and Engineering, the Chinese University of Hong Kong and Ph.D. degree in computer engineering at the Department of Electrical Engineering, Texas A&M University.