Title: Early Global Route Planning
Speaker: Prof. Susmita Sur-Kolay, Indian Statistical Institute
DATE:104年05月29日(星期五)上午十點三十分-十二
PLACE:資電館R550
HOST:王廷基 老師
Abstract:
Physical design of a chip typically entails the global routing (GR) step after detailed placement. In this step, the grid graph (GG) model is used widely for the one or two-bend pattern routing stage. In order to reduce the number of iterations required for congestion-aware GR,early route planning is proposed. The routing regions can be identified as recursive top-down bipartitioning by either straight cutlines or monotone staircases. The capacity of each region is estimated as the number nets that can fit in it without design rule violation. Given a floorplan, identifying a set of monotone staircases such that (a) the balance in area of each bipartition is maximized, (b) the number of nets cut, and (c) the number of bends in a monotone staircase are minimized, is a multi-objective NP-hard optimization problem. The existing heuristic methods are based on either maxflow or directed search on floorplan adjacency graph. We propose an early global route planning for a given floorplan with an efficient monotone staircase bipartitioning method followed by a global router for monotone staircase channels with minimal congestion.
Speaker Bio:
Susmita Sur-Kolay is presently a Professor in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India. Her research contributions are in the areas of algorithms for design automation, Intellectual Property protection of electronic design, synthesis of quantum computers, graph algorithms. She has authored several technical papers in international journals and refereed conference proceedings and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She has served on the program committees of many international conferences and was the Technical Program Co-Chair for three of them. She is an Associate Editor of ACM Transactions on Embedded Computing Systems and was on the editorial board of Proc. of IEE CDT and IEEE Transactions on VLSI Systems. She was a Distinguished Visitor of IEEE Computer Society(India), is a Senior Member of IEEE, and Member of ACM. Two papers co-authored by her won best paper awards at two international conferences. Among other awards, she was the recipient of the President of India Gold Medal at IIT Kharagpur and IBM Faculty Award.