Biography

Dr. Hao Yu obtained Ph. D degree from electrical engineering department at UCLA in 2007. 

Since 2010, he has been a faculty at school of electrical and electronic engineering and area directors 

at VIRTUS (IC design) and Valens (biomedical) centre of excellence, Nanyang Technological University 

(NTU), Singapore. His primary research interest is in CMOS emerging technology for energy-efficient 

accelerators, links and sensors with more than 4M-USD research funding from agency and industry 

(Intel, Oracle, Huawei, TSMC). He has ~160 peer-reviewed IEEE/ACM publications, 4 books, 1 best 

paper award of ACM Transaction, 2 keynote talks, 3 best paper award nominations, 3 student paper 

competition (advisor) finalists, 1 inventor award from semiconductor research cooperation (SRC), and 

15 patents. He is associate editor and technical program committee member of many IEEE/ACM 

international journals and conferences. He is a senior member of IEEE and member of ACM. 

Abstract 

Big-data analytics has scaled up to Exa-scale that is already beyond the scalability of the present 

technology and architecture. It has thereby raised many new research opportunities to deploy emerging 

technology and architecture towards building a data server on chip with integrated 1000-acclerator-core 

and main memory. One fundamental challenge is how to overcome dark silicon dilemma with improved I/O 

utilization for both power management and data communication. Firstly, we discuss a 2.5D through-

silicon-interposer reconfigurable I/O (connection and voltage swing) architecture developed for both 

scalable power management and data communication in data-server with results reported in DAC’13, 

ICCAD’14, and CICC’15, where on-chip data analytics is deployed to learn data pattern such that I/Os can 

be configured for energy-efficient data migration. Secondly, we discuss a non-volatile in-memory 

(machine-learning) architecture without I/Os. According energy-efficient online machine-learning 

accelerators (direct L2-norm solution) are developed in both CMOS and memristor with results reported 

in DATE’15, ISLPED’15 and VLSI-SYMP’15.