Abstract

The emerging security threats in the IC supply chain do not only challenge chip integrity, but also raise serious concerns on hardware Intellectual Property (IP) piracy. Existing register-transfer level hardware obfuscation methods for 2D integrated circuits (ICs) insert a key sequence in the control and data flow to prevent attackers from accessing the normal operation mode of a chip, rather than protecting state transitions in the normal operation mode. We propose a low-cost state-deflection based obfuscation method, in which we utilize a state rotation function and selective register flipping function to dynamically control the state deflection paths. As a result, we significantly increase the difficulty of reverse engineering and thwart register attacks on 2D ICs.

Three-dimensional (3D) integration has attracted significant attention during the past two decades to develop diverse computing platforms. Despite the well-understood advantages over 2D integrated circuits (ICs), 3D ICs introduce unique and unexplored challenges on managing hardware security. We propose a novel 3D obfuscation method to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. We further propose a novel method for transistor level logic locking to address IP piracy and reverse engineering attacks in monolithic three-dimensional (M3D) ICs. The proposed method locks logic gates by independently inserting parallel or serial locking transistors and camouflaged contacts in multiple tiers in M3D ICs. Without the correct key bits and confidential information for camouflaged contacts, the locked logic gates will malfunction and significantly alter power profiles, which makes reverse engineering attacks more difficult.

Bio

Dr. Qiaoyan Yu received a B.S. degree in Communication Engineering from Xidian University, China (2002), obtained a M.S. degree in Communication and Information Engineering from Zhejiang University, China (2005), and received her a Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in 2011. Currently, Dr. Yu is with the department of Electrical and Computer Engineering at the University of New Hampshire.  She serves on the technical program committees of DFT, ASP-DAC, GLSVLSI, ISCAS, and HOST.  Dr. Yu also serves on the editorial boards of Integration, the VLSI Journal, Microelectronics Journal, and Journal of Circuits, Systems, and Computers. Dr. Yu’s research interests include hardware security and trust, cyber-physical system, error control for networks-on-chip, fault-tolerance for many-core systems, and emerging nanoelectronics. 

All faculties and students are welcome to join.