Abstract

As the number of memories in a chip has grown to hundreds of thousands, especially for AI, mobile, and HPC-related applications, the complexity of searching for good floorplans is significantly increasing. To tackle the searching complexity, automatic floorplanning for various objectives is required. With the recent advances in artificial intelligence, we apply reinforcement learning and hyperparameter tuning techniques to explore floorplan possibilities intelligently. Our AI-assisted dataflow-driven floorplan exploration tool, MaxPlace, can effectively reduce the design iteration cycles and significantly improve performance, power, area, and schedule (PPAS).

Bio.

Tung-Chieh Chen received his B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), in 2003 and 2008, respectively. He is a co-founder and Chief Executive Officer of Maxeda Technology since 2015. He was a visiting scholar at the University of Texas at Austin in 2007. He joined SpringSoft (2008-2012) and then entered Synopsys (2012-2015) by acquisition.
Dr. Chen is a recipient of the 2021 Design Automation Conference Under-40 Innovators Award. He was the first place winner in the 2007 ACM SIGDA CADathlon Contest. He received the Best Dissertation Award from the Graduate Institute of Electronics Engineering (GIEE) at NTU in 2008, the Electronic Elite Special Contribution Award from GIEE at NTU in 2017.  He has published 12 IEEE Transactions on CAD journal papers, 26 IEEE/ACM conference papers, and 14 US patents, all on VLSI floorplanning and placement. Dr. Chen has served as a technical committee member for ISPD, ICCAD, ASP-DAC, and DAC.

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