Abstract

As AI and big data applications scale in model complexity and dataset size, the bottleneck has shifted from computation to data movement across compute, memory, and storage layers. This talk presents a cross-layer, co-designed approach to accelerate big data workloads by rethinking memory hierarchies and compute accelerators. I will discuss how my group addresses the novel memory systems (e.g., SCM-aware graph layout, SSD-augmented memory via SyncIO-Swap), and compute accelerators (e.g., KV cache scheduling in LLMs, and PIM-assisted ANN search). Through a unified lens of minimizing unnecessary data transfers, this work demonstrates significant speedups and resource efficiency across diverse platforms, positioning co-design as a central strategy in next-generation system architecture.

Bio.

Chun-Feng Wu(吳俊峯) is an assistant professor at National Yang Ming Chiao Tung University. He was a postdoctoral scholar in Department of Computer Science, Harvard University from 2021 to 2022. He received his M.S. and Ph.D. degree in Department of Computer Science from National Tsing Hua University, in 2016 and in Department of Computer Science and Information Engineering from National Taiwan University in 2021 respectively. His primary research interests include memory/storage systems, embedded systems, operating systems and the next-generation memory/storage architecture. Received Awards: Yushan Young Fellow (教育部玉山青年學者), 2030 Emerging Young Scholars (國科會新秀學者), K. T. Li Young Researcher Award (2024 李國鼎青年研究獎), Semiconductor Award (2025 台灣半導體產業協會半導體獎), Macronix Scholar Award(旺宏電子學者)

All faculty and students are welcome to join.