Abstract

As chip complexity grows and technology nodes advance, artificial intelligence is becoming an important approach to improving the efficiency and quality of electronic design automation (EDA). This talk explores two AI applications in VLSI physical design. First, it presents reinforcement learning for macro placement, combining netlist connectivity and spatial layout information through multimodal feature fusion to learn placement policies that reduce wirelength while satisfying legality constraints. Second, it introduces CNN-based design rule violation prediction, using global-routing congestion and placement features to predict violation distributions after detailed routing. By addressing class imbalance in training data, this approach helps identify high-risk regions early and reduce costly design iterations. Together, these studies illustrate how domain knowledge, data representations, and learning strategies enable AI-driven optimization and quality prediction in chip design.

Bio.

Dr. Andy, Yu-Guang Chen received the B.S. degree and Ph.D. degree in Dept. of Computer Science from National Tsing Hua University, Hsinchu, Taiwan, in 2009 and 2016, respectively. He worked as a Lecturer at Missouri University of Science and Technology, MO, USA in 2015, and a research fellow at University of Notre Dame, IN, USA as in 2016. After that, he served as a project assistant of the ICT project at St. Kitts and Nevis with ICDF Taiwan from 2016 to 2017. He joined the Department of Computer Science and Engineering, Yuan Ze University from 2017 to 2019, and Department of Electrical Engineering, National Central University, from 2019 to 2026. He is currently an associate professor with Department of Electrical Engineering, National Tsgin Hua University. Professor Chen has published several technical papers and has served in the several program committees such as ISVLSI, ASP-DAC, CSTIC, and is now an co-chair of The CAD Contest at ICCAD and CADathlon at ICCAD. His current research interests include aging-aware design optimization and tolerance, Reliable In-Memory Computing (IMC) design, Power Distribution Network (PDN) Design and Optimization, Hardware accelerator for edge devices, and Hardware Security.

All faculty and students are welcome to join.