Pushing Multiple Patterning and Hybrid Lithography in Sub-10nm: What’s the Limit?
Speaker: David Z. Pan, The University of Texas at Austin, USA
DATE:104年09月01日(星期二)上午九點二十分
PLACE:台達館A615
HOST:王廷基 老師
Abstract:
Due to elongated delay of extreme ultraviolet (EUV) lithography, the semiconductor industry has been pushing the 193nm immersion lithography using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. This talk will discuss the current state of the art of the MPL research, from mask synthesis to physical design. We will also discuss its role in the hybrid lithography with other emerging lithography technologies such as DSA, e-beam and EUV, to push multiple patterning to the extreme.
Speaker Bio:
David Z. Pan received his BS degree from Peking University, and MS/PhD degrees from UCLA. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently the Engineering Foundation Professor at The University of Texas at Austin. He has published over 220 refereed journal and conference papers and holds 8 US patents. He has served in many journal editorial boards (e.g., TCAD, TVLSI, TCAD-I, TCAS-II, TODAES, SCIS) and conference organizing/program committees (DAC, ICCAD, DATE, ASPDAC, ISLPED, ISPD, etc.). He is currently a Senior Associate Editor for TODAES, ASP-DAC 2016 TPC Vice Chair, and ICCAD 2015 Workshop Chair.
He has received a number of awards, including the SRC 2013 Technical Excellence Award, 11 Best Paper Awards, DAC Top 10 Author Award in Fifth Decade, DAC Prolific Author Award, ASP-DAC Frequently Cited Author Award, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD’12 and ICCAD’13 CAD Contest Awards, among others. He is an IEEE Fellow.
DATE:104年09月01日(星期二)上午九點二十分
PLACE:台達館A615
HOST:王廷基 老師
Abstract:
Due to elongated delay of extreme ultraviolet (EUV) lithography, the semiconductor industry has been pushing the 193nm immersion lithography using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. This talk will discuss the current state of the art of the MPL research, from mask synthesis to physical design. We will also discuss its role in the hybrid lithography with other emerging lithography technologies such as DSA, e-beam and EUV, to push multiple patterning to the extreme.
Speaker Bio:
David Z. Pan received his BS degree from Peking University, and MS/PhD degrees from UCLA. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently the Engineering Foundation Professor at The University of Texas at Austin. He has published over 220 refereed journal and conference papers and holds 8 US patents. He has served in many journal editorial boards (e.g., TCAD, TVLSI, TCAD-I, TCAS-II, TODAES, SCIS) and conference organizing/program committees (DAC, ICCAD, DATE, ASPDAC, ISLPED, ISPD, etc.). He is currently a Senior Associate Editor for TODAES, ASP-DAC 2016 TPC Vice Chair, and ICCAD 2015 Workshop Chair.
He has received a number of awards, including the SRC 2013 Technical Excellence Award, 11 Best Paper Awards, DAC Top 10 Author Award in Fifth Decade, DAC Prolific Author Award, ASP-DAC Frequently Cited Author Award, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD’12 and ICCAD’13 CAD Contest Awards, among others. He is an IEEE Fellow.